1. Field of the Invention
The present invention relates to static random access memory (SRAM) devices with resistor loads, and, more particularly, to an improved method for forming the polysilicon resistor load (poly load) which is scalable to smaller dimensions.
2. Description of the Related Art
SRAMs with resistor loads employ polysilicon as the resistance material, since by ion implantation, its resistance can be controlled to greater than 10.sup.9 ohms per square. The polysilicon resistors can be made in the same single layer of polysilicon (gate and interconnect) by masking the polysilicon resistor regions from the high-impurity doping used in the gate and interconnect portions of the polysilicon layer. Additional area can be saved by using a second layer of polysilicon for the load resistors, and overlaying these resistors on the active area of the cell, as described in Sze, VLSI Technology, McGraw-Hill, pages 474-476 (1983).
However, such a dual polysilicon configuration, in which the two polysilicon layers are separated by chemically vapor deposited silicon dioxide, requires two extra masking steps, namely, the formation of an inter-poly contact that joins the load to the drain of the crosscoupled transistors and a poly load feature mask. In some applications, a third mask is used to define the load so that the second poly configuration can have both low resistance and high resistance at the same time. In this type of layout, the minimum length of the poly load will be critical. The load length cannot be too short, or else the load will be electrically shorted by lateral diffusion of the dopant from the highly doped, low resistance region into the lightly doped, high resistance region. The minimum poly load region depends on the process back-end temperature cycle; typically it is in the 4 to 6 micrometer region. A length shorter than this will impair the yield. Thus, scaling to the next generation of SRAMs will be limited by the ability of making short length poly resistors.
Additional problems that occur with prior art fabrication of SRAMs is that the dual poly structure results in poor step coverage. Further, the aspect ratio (step height divided by aperture size) of the contacts is poor. Due to the fact that dual poly is employed with the required isolation between the two poly layers and metal, the step height of a typical metal contact will be at least 0.8 to 1.5 micrometers, depending on the process to delineate the topology. With a typical contact aperture of about 1.2 micrometers for the state of the art contact opening, the aspect ratio will be about 1. The metal interconnect will not be able to make a better than 50% step coverage (which is a requirement of certain military specifications).
Thus, it is clear that a process for fabricating a polysilicon resistor load in a SRAM which avoids most, if not all, the foregoing problems is required.